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copyright ? cirrus logic, inc. 2010 (all rights reserved) http://www.cirrus.com august '10 ds685f3 108 db, 192 khz 4-in, 8-out tdm codec features ? four 24-bit a/d, eight 24-bit d/a converters ? adc dynamic range ? 105 db differential ? 102 db single-ended ? dac dynamic range ? 108 db differential ? 105 db single-ended ? adc/dac thd+n ? -98 db differential ? -95 db single-ended ? compatible with industry-standard time division multiplexed (t dm) serial interface ? dac sampling rates up to 192 khz ? adc sampling rates up to 96 khz ? programmable adc high-pa ss filter for dc offset calibration ? logarithmic digital volume control ? hardware mode or software i2c ? & sp i ? ? supports logic levels between 5 v and 1.8 v general description the cs42435 codec provides four multi-bit analog-to- digital and eight multi-bit digital-to-analog delta-sigma converters. the codec is capable of operation with ei- ther differential or single-e nded inputs and outputs, in a 52-pin mqfp package. four fully differential, or single-ended, inputs are avail- able on stereo adc1 and a dc2. digital volume control is provided for each adc channel, with selectable over- flow detection. an auxiliary serial input is available for an additional two channels of pcm data. all eight dac channels provide digital volume control and can operate with differential or single-ended outputs. the cs42435 is available in a 52-pin mqfp package in commercial (-40c to +85c) and automotive (-40c to +105c) grades. the cdb42438 customer demonstra- tion board is also available for device evaluation and implementation suggestions. please refer to ?ordering information? on page 57 for complete ordering information. the cs42435 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as a/v receivers, dvd receivers, and automotive audio systems. control port & serial audio port supply = 1.8 v to 5 v register configuration internal voltage reference reset tdm serial interface level translator level translator tdm serial audio input digital supply = 3.3 v hardware mode or i 2 c/spi software mode control data analog supply = 3.3 v to 5 v differential or single-ended outputs 8 input master clock 8 tdm serial audio output multibit oversampling adc1 high pass filter differential or single-ended analog inputs 2 digital filters 2 multibit oversampling adc2 high pass filter 2 digital filters 2 auxilliary serial audio input volume controls digital filters multibit dac1-4 and analog filters ?? modulators cs42435
2 ds685f3 cs42435 table of contents 1. pin descriptions - software mode .................................................................................... 6 1.1 digital i/o pin characteristics ........................................................................................... ................ 8 2. pin descriptions - hardware mode........................................................................................... 9 3. typical connection diagrams ...................................................................................... .11 4. characteristics and specificat ions........... ................. ................................................ ......... 13 recommended operating conditions ................................................................................... 13 absolute maximum rating s ................ ................. ................................ .......................... ........... .13 analog input characteristics (commercial) .................................................................... 14 analog input characteristics (automotive) .. ................................................................... 15 adc digital filter characteristics ....................................................................................... 16 analog output characteristics (commercial) ................................................................ 17 analog output characteristics (automotive) ................................................................. 18 combined dac interpolation & on-chip analog filter response .............................. 20 switching specifications - adc/dac port ............................................................................ 21 switching characteristics - aux port ................................................................................. 22 switching specifications - control port - i2c mode ....................................................... 23 switching specifications - control port - spi format ................................................. 24 dc electrical characteristics .............................................................................................. 25 digital interface specifications & character istics ..................................................... 25 5. applications ................................................................................................................ .................... 26 5.1 overview .................................................................................................................. ....................... 26 5.2 analog inputs ............................................................................................................. ..................... 27 5.2.1 line-level inputs ....................................................................................................... ............ 27 5.2.1.1 hardware mode ......... ................................................................................................ 27 5.2.1.2 software mode ......................................................................................................... .. 27 5.2.2 high-pass filter and dc offset calibration ........................................................................... 27 5.2.2.1 hardware mode ......... ................................................................................................ 28 5.3 analog outputs ............................................................................................................ ................... 28 5.3.1 initialization .......................................................................................................... .................. 28 5.3.2 line-level outputs and filtering ........................................................................................ .... 28 5.3.3 digital volume control .................................................................................................. ......... 30 5.3.3.1 hardware mode ......... ................................................................................................ 30 5.3.3.2 software mode ......................................................................................................... .. 30 5.3.4 de-emphasis filter ...................................................................................................... .......... 30 5.4 system clocking ........................................................................................................... .................. 31 5.4.1 hardware mode ........................................................................................................... .......... 31 5.4.2 software mode ........................................................................................................... ........... 31 5.5 codec digital interface ................................................................................................... .............. 31 5.5.1 tdm ..................................................................................................................... .................. 31 5.5.2 i/o channel allocation .................................................................................................. ......... 32 5.6 aux port digital interface formats ........................................................................................ ......... 32 5.6.1 hardware mode ........................................................................................................... .......... 32 5.6.2 software mode ........................................................................................................... ........... 32 5.6.3 i2s ..................................................................................................................... ..................... 32 5.6.4 left-justified .......................................................................................................... ................ 33 5.7 control port descripti on and timing ....................................................................................... ........ 33 5.7.1 spi mode ................................................................................................................ ............... 33 5.7.2 i2c mode ................................................................................................................ ................ 34 5.8 recommended power-up sequen ce ............................................................................................. 35 5.8.1 hardware mode ........................................................................................................... .......... 35 5.8.2 software mode ........................................................................................................... ........... 36 5.9 reset and power-up ......... ............................................................................................... .............. 36
ds685f3 3 cs42435 5.10 power supply, grounding, and pcb layout ................................................................................. 3 6 6. register quick reference .................................................................................................... ..... 37 7. register description ........................................................................................................ ........... 39 7.1 memory address poin ter (map) .............................................................................................. ....... 39 7.1.1 increment (incr) ........................................................................................................ .......... 39 7.1.2 memory address pointer (map[6:0]) ..................................................................................... 39 7.2 chip i.d. and revision regist er (address 01h) (read only) .......................................................... 39 7.2.1 chip i.d. (chip_id[3:0]) ................................................................................................ ........ 39 7.2.2 chip revision (rev_id[3:0]) ................. ............................................................................ .... 39 7.3 power control (address 02h) ...................... ......................................................................... .......... 40 7.3.1 power down adc pairs (pdn_adcx) ........... ...................................................................... 40 7.3.2 power down dac pairs (pdn_dacx) ........... ...................................................................... 40 7.3.3 power down (pdn) ........................................................................................................ ....... 40 7.4 functional mode (address 03h) ............................................................................................. ......... 41 7.4.1 mclk frequency (mfreq[2:0]) ........................................................................................... 41 7.5 miscellaneous control (address 04h) ............. .......................................................................... ...... 41 7.5.1 freeze controls (freeze) ................................................................................................ ... 41 7.5.2 auxiliary digital interface format (aux_dif) ........................................................................ 41 7.6 adc control & dac de-emphasis (address 05h) ......................................................................... 42 7.6.1 adc1-2 high-pass filter freeze (adc1-2_hpf freeze) ..... ............................................. 42 7.6.2 dac de-emphasis control (d ac_dem) ............................................................................... 42 7.6.3 adc1 single-ended mode (adc1 single) ......................................................................... 42 7.6.4 adc2 single-ended mode (adc2 single) ......................................................................... 43 7.7 transition control (address 06h) ................. ......................................................................... .......... 43 7.7.1 single volume control (dac_sngvol, ad c_sngvol) .................................................... 43 7.7.2 soft ramp and zero cross control (adc_s zc[1:0], dac_szc[1:0]) .................................. 43 7.7.3 auto-mute (amute) ....................................................................................................... ....... 44 7.7.4 mute adc serial port (mute adc_sp) ..... .......................................................................... 44 7.8 dac channel mute (address 07h) ............................................................................................ ..... 44 7.8.1 independent channel mute (aoutx_mute) ....................................................................... 44 7.9 aoutx volume control (addresse s 08h- 0fh) .......................................................................... 45 7.9.1 volume control (aoutx_vol [7:0]) ...................................................................................... 45 7.10 dac channel invert (address 10h) ......................................................................................... ..... 45 7.10.1 invert signal polarity (inv_aoutx) ....... ............................................................................. 4 5 7.11 ainx volume control (address 11h-14h) ..... ............................................................................... .45 7.11.1 ainx volume control (ainx_vol[7:0]) .............................................................................. 45 7.12 adc channel invert (address 17h) ......................................................................................... ..... 46 7.12.1 invert signal polarity (inv_ainx) ...................................................................................... .. 46 7.13 status (address 19h) (read only) ......................................................................................... ....... 46 7.13.1 clock error (clk error) ..................... ........................................................................... .. 46 7.13.2 adc overflow (adcx_ovfl) ....................... ...................................................................... 46 7.14 status mask (address 1ah) ................................................................................................ .......... 47 8. external filters............................................................................................................ ................ 48 8.1 adc input filter .......................................................................................................... .................... 48 8.1.1 passive input filter .................................................................................................... ............ 49 8.1.2 passive input filter w/attenuation ...................................................................................... ... 49 8.2 dac output filter ......................................................................................................... .................. 50 9. adc filter plots............................................................................................................ ................. 51 10. dac filter plots........................................................................................................... ................ 53 11. parameter definitions...................................................................................................... ......... 55 12. referen ces................................................................................................................. .................... 55 13. package information........................................................................................................ ......... 56 13.1 thermal characteristics .................................................................................................. ............. 56 14. ordering information ....................................................................................................... ........ 57
4 ds685f3 cs42435 15. revision history ........................................................................................................... ................ 57 list of figures figure 1.typical connection diagram (software mode) ........................................................................... 11 figure 2.typical connection diagram (hardware mode) .......................................................................... 1 2 figure 3.output test circuit for maximum load ................................................................................. ...... 19 figure 4.maximum loading ...................................................................................................... ................. 19 figure 5.tdm serial audio interface timing ...... .............................................................................. ......... 21 figure 6.serial audio interface slave mode timing ............................................................................. ..... 22 figure 7.control port timing - i2c format ..................................................................................... ............ 23 figure 8.control port timing - spi format ..................................................................................... ........... 24 figure 9.full-scale input ..................................................................................................... ...................... 27 figure 10.audio output initialization flow chart .............................................................................. ......... 29 figure 11.full-scale output ................................................................................................... ................... 30 figure 12.de-emphasis curve ................................................................................................... ............... 31 figure 13.tdm serial audio format ............... .............................................................................. ............ 32 figure 14.aux i2s format ............................ .......................................................................... ................... 32 figure 15.aux left-justified format ........................................................................................... .............. 33 figure 16.control port timing in spi mode ....... .............................................................................. ......... 34 figure 17.control port timing, i2c write ......... ............................................................................. ............. 34 figure 18.control port timing, i2c read ......... .............................................................................. ............ 35 figure 19.single-to-diffe rential active input filter .......................................................................... ........... 48 figure 20.single-en ded active input filter .................................................................................... ............ 48 figure 21.passive input filter ................................................................................................ ................... 49 figure 22.passive input filter w/attenuation .................................................................................. ........... 49 figure 23.active analog output filter ......................................................................................... .............. 50 figure 24.passive analog output filter ....... ................................................................................. ............ 50 figure 25.ssm stopband rejection .............................................................................................. ............ 51 figure 26.ssm transition band ................................................................................................. ............... 51 figure 27.ssm transition band (detail) ........................................................................................ ........... 51 figure 28.ssm passband ripple ................................................................................................. ............. 51 figure 29.dsm stopband rejection .............................................................................................. ............ 51 figure 30.dsm transition band ................................................................................................. ............... 51 figure 31.dsm transition band (detail) ......... ............................................................................... ........... 52 figure 32.dsm passband ripple ................................................................................................. ............. 52 figure 33.ssm stopband rejection .............................................................................................. ............ 53 figure 34.ssm transition band ................................................................................................. ............... 53 figure 35.ssm transition band (detail) ........................................................................................ ............ 53 figure 36.ssm passband ripple ................................................................................................. ............. 53 figure 37.dsm stopband rejection .............................................................................................. ............ 53 figure 38.dsm transition band ................................................................................................. ............... 53 figure 39.dsm transition band (detail) ....... ................................................................................. ............ 54 figure 40.dsm passband ripple ................................................................................................. ............. 54 figure 41.qsm stopband rejection .............................................................................................. ........... 54 figure 42.qsm transition band ................................................................................................. ... ............ 54 figure 43.qsm transition band (detail) ........................................................................................ ............ 54 figure 44.qsm passband ripple ................................................................................................. ............. 54
ds685f3 5 cs42435 list of tables table 1. i/o power rails ...................................................................................................... ....................... 8 table 2. hardware config urable settings ....................................................................................... .......... 26 table 3. mclk frequency settings .............................................................................................. ............ 31 table 4. serial audio interface channel allocations .... ....................................................................... ...... 32 table 5. mclk frequency settings .............................................................................................. ............ 41 table 6. example aout volume se ttings ......................................................................................... ....... 45 table 7. example ain volume settings ............. ............................................................................. .......... 46
6 ds685f3 cs42435 1. pin descriptions - software mode pin name # pin description scl/cclk 1 serial control port clock (input ) - serial clock for the control port interface. sda/cdout 2 serial control data i/o ( input/output ) - input/output for i2c data. output for spi data. ad0/cs 3 address bit [0]/ chip select ( input ) - chip address bit in i2c mode. control signal used to select the chip in spi mode. ad1/cdin 4 address bit [1]/ spi data input ( input ) - chip address bit in i2c mode. input for spi data. rst 5 reset ( input ) - the device enters a low-power mode and all internal registers are reset to their default settings when low. vlc 6 control port power (input ) - determines the required signal level for the control port interface. see ?digital i/o pin characteristics? on page 8 . fs 7 frame sync ( input ) - signals the start of a new tdm frame in the tdm digital interface format. vd 8 digital power ( input ) - positive power supply for the digital section. dgnd 9,18 digital ground ( input ) - ground reference for the digital section. vls 10 serial port interface power ( input ) - determines the required signal le vel for the serial port inter- faces. see ?digital i/o pin characteristics? on page 8 . sclk 11 serial clock (input) - serial clock for the serial audio interface. input frequency must be 256 x fs. mclk 12 master clock ( input ) - clock source for the delta-sigm a modulators and digital filters. adc_sdout 13 serial audio data output (output) - tdm output for two?s complement serial audio data. dac_sdin 14 dac serial audio data input ( input ) - tdm input for two?s complement serial audio data. aux_lrck 15 auxiliary left/right clock ( output ) - determines which channel, left or right, is currently active on the auxiliary serial audio data line. 6 2 4 8 10 1 3 5 7 9 11 12 14 15 16 17 18 19 20 21 22 23 24 25 33 37 35 31 29 38 36 34 32 30 28 27 52 51 50 49 48 47 46 45 44 43 42 41 vls fs mclk vlc filt+ aout5+ aout3+ agnd va aux_sdin dac_sdin adc_sdout aux_sclk aux_lrck aout4+ rst aout6+ aout3- va agnd aout2+ aout2- aout1- aout1+ dgnd vd sclk dgnd vq tstn tstn aout6- aout4- 13 26 39 aout5- 40 ain3+ ain4- ain4+ tstn ain3- tstn ain1+ ain2- ain2+ ain1- scl/cclk ad1/cdin ad0/cs sda/cdout aout7+ aout8+ aout8- aout7- cs42435
ds685f3 7 cs42435 aux_sclk 16 auxiliary serial clock (output) - serial clock for the auxiliary serial audio interface. aux_sdin 17 auxiliary serial input ( input ) - the cs42435 provides an additional serial input for two?s comple- ment serial audio data. aout1 +,- aout2 +,- aout3 +,- aout4 +,- aout5 +,- aout6 +,- aout7 +,- aout8 +,- 20,19 21,22 24,23 25,26 28,27 29,30 32,31 33,34 differential analog output ( output ) - the full-scale differential ana log output level is specified in the analog characteristics specif ication table. each positive leg of the differential outputs may also be used single-ended. tstn 49,50 51,52 test in - these pins are inputs used for test purposes only. they must be tied to ground for nor- mal operation. agnd 35,48 analog ground ( input ) - ground reference for the analog section. vq 36 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage. va 37,46 analog power ( input ) - positive power supply for the analog section. ain1 +,- ain2 +,- ain3 +,- ain4 +,- 39,38 41,40 43,42 45,44 differential analog input ( input ) - signals are presented differenti ally to the delta-sigma modula- tors. the full-scale input level is specified in the analog characteristics specification table. filt+ 47 positive voltage reference ( output ) - positive reference voltage for the internal sampling cir- cuits.
8 ds685f3 cs42435 1.1 digital i/o pin characteristics various pins on the cs42435 are powered from separate power supply rails. the logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings. power rail pin name sw/(hw) i/o driver receiver vlc rst input - 1.8 v - 5.0 v, cmos scl/cclk (test) input - 1.8 v - 5.0 v, cmos, with hysteresis sda/cdout (test) input/ output 1.8 v - 5.0 v, cmos/open drain 1.8 v - 5.0 v, cmos, with hysteresis ad0/cs (mfreq) input - 1.8 v - 5.0 v, cmos ad1/cdin (test) input - 1.8 v - 5.0 v, cmos vls mclk input - 1.8 v - 5.0 v, cmos lrck input - 1.8 v - 5.0 v, cmos sclk input - 1.8 v - 5.0 v, cmos adc_sdout input/ output 1.8 v - 5.0 v, cmos - dac_sdin input - 1.8 v - 5.0 v, cmos aux_lrck output 1.8 v - 5.0 v, cmos - aux_sclk output 1.8 v - 5.0 v, cmos - aux_sdin input - 1.8 v - 5.0 v, cmos table 1. i/o power rails
ds685f3 9 cs42435 2. pin descriptions - hardware mode pin name # pin description test 1,2,4 test - these pins are inputs used for test purposes only. they must be tied high or low. mfreq 3 mclk frequency ( input ) - sets the required frequency r ange of the input master clock. rst 5 reset ( input ) - the device enters a low-power mode and a ll internal registers are reset to their default settings when low. vlc 6 control port power ( input ) - determines the required signal level for the control port interface. see ?digital i/o pin characteristics? on page 8 . fs 7 frame sync ( input ) - signals the start of a new tdm frame in the tdm digital interface format. vd 8 digital power ( input ) - positive power supply for the digital section. dgnd 9,18 digital ground ( input ) - ground reference for the digital section. vls 10 serial port interface power ( input ) - determines the required signal level for the serial port inter- faces. see ?digital i/o pin characteristics? on page 8 . sclk 11 serial clock (input) - serial clock for the serial audio interface. input frequency must be 256 x fs. mclk 12 master clock ( input ) - clock source for the delta-sigma modulators and digital filters. adc_sdout 13 serial audio data output (output) - tdm output for two?s complement serial audio data. dac_sdin 14 dac serial audio data input ( input ) - tdm input for two?s complement serial audio data. aux_lrck 15 auxiliary left/right clock ( output ) - determines which channel, left or right, is currently active on the auxiliary serial audio data line. aux_sclk 16 auxiliary serial clock (output) - serial clock for the auxiliary serial audio interface. aux_sdin 17 auxiliary serial input ( input ) - the cs42435 provides an additional serial input for two?s comple- ment serial audio data. test 6 2 4 8 10 1 3 5 7 9 11 12 14 15 16 17 18 19 20 21 22 23 24 25 33 37 35 31 29 38 36 34 32 30 28 27 52 51 50 49 48 47 46 45 44 43 42 41 vls fs mclk vlc test filt+ aout5+ aout3+ agnd va aux_sdin dac_sdin adc_sdout aux_sclk aux_lrck mfreq aout4+ rst aout6+ aout3- va agnd aout2+ aout2- aout1- aout1+ dgnd vd sclk dgnd vq aout6- aout4- 13 test 26 39 aout5- 40 ain3+ ain4- ain4+ ain3- ain1+ ain2- ain2+ ain1- tstn tstn tstn tstn aout7+ aout8+ aout8- aout7- cs42435
10 ds685f3 cs42435 aout1 +,- aout2 +,- aout3 +,- aout4 +,- aout5 +,- aout6 +,- aout7 +,- aout8 +,- 20,19 21,22 24,23 25,26 28,27 29,30 32,31 33,34 differential an alog output ( output ) - the full-scale differential analog output level is specified in the analog characteristics specif ication table. each positive l eg of the differential outputs may also be used single-ended. agnd 35,48 analog ground ( input ) - ground reference for the analog section. vq 36 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage. va 37,46 analog power ( input ) - positive power supply for the analog section. ain1 +,- ain2 +,- ain3 +,- ain4 +,- 39,38 41,40 43,42 45,44 differential analog input ( input ) - signals are presented differentially to the delta-sigma modula- tors. the full-scale input level is specified in the analog characteristics specification table. filt+ 47 positive voltage reference ( output ) - positive reference voltage for the internal sampling cir- cuits. tstn 49,50 51,52 test in - these pins are inputs used for test purposes only. they must be tied to ground for nor- mal operation.
ds685f3 11 cs42435 3. typical connection diagrams 100 f 0.1 f + + vq filt+ 0.1 f 4.7 f va 0.01 f dgnd digital audio processor cs5341 a/d converter va vd agnd agnd connect dgnd and agnd at codec 0.01 f + 10 f 0.01 f +3.3 v + 10 f 0.01 f +1.8 v to +5.0 v 1. see the adc input filter section in the appendix. 2. see the dac output filter section in the appendix. +3.3 v to +5 v dgnd aout1+ aout1- aout2+ aout2- aout3+ aout3- aout4+ aout4- analog output filter 2 analog output filter 2 analog output filter 2 aout5+ aout5- aout6+ aout6- analog output filter 2 analog output filter 2 analog output filter 2 0.1 f +1.8 v to +5 v micro- controller 2 k ? 2 k? ** ** ** resistors are required for i 2 c control port operation analog input 1 analog input 2 ain3+ ain1+ ain1- ain2+ ain2- ain3- ain4+ ain4- analog input 3 analog input 4 input filter 1 input filter 1 input filter 1 input filter 1 17 16 10 15 13 14 7 11 12 5 6 9 48 35 18 47 37 44 45 42 43 40 41 38 39 30 29 27 28 26 25 23 24 22 21 19 20 46 37 8 1 2 4 3 vls mclk aux_sdin dac_sdin fs sclk aux_sclk aux_lrck adc_sdout vlc scl/cclk rst ad0/cs sda/cdout ad1/cdin aout7+ aout7- aout8+ aout8- analog output filter 2 analog output filter 2 34 33 31 32 figure 1. typical connection diagram (software mode)
12 ds685f3 cs42435 100 f 0.1 f + + vq filt+ 0.1 f 4.7 f va 0.01 f dgnd 0.1 f digital audio processor cs5341 a/d converter va vd agnd agnd connect dgnd and agnd at codec 0.01 f + 10 f 0.01 f +3.3 v + 10 f 0.01 f +1.8 v to +5.0 v 1. see the adc input filter section in the appendix. 2. see the dac output filter section in the appendix. analog input 1 analog input 2 ain3+ +3.3 v to +5 v dgnd ain1+ ain1- ain2+ ain2- ain3- ain4+ ain4- analog input 3 analog input 4 input filter 1 aout1+ aout1- aout2+ aout2- aout3+ aout3- aout4+ aout4- analog output filter 2 analog output filter 2 analog output filter 2 aout5+ aout5- aout6+ aout6- analog output filter 2 analog output filter 2 analog output filter 2 input filter 1 input filter 1 input filter 1 17 16 10 15 13 14 7 11 12 3 5 6 9 48 35 18 47 37 44 45 42 43 40 41 38 39 30 29 27 28 26 25 23 24 22 21 19 20 46 37 8 vlc rst mfreq vls mclk aux_sdin dac_sdin fs sclk aux_sclk aux_lrck adc_sdout aout7+ aout7- aout8+ aout8- analog output filter 2 analog output filter 2 34 33 31 32 figure 2. typical connection diagram (hardware mode)
ds685f3 13 cs42435 4. characteristics an d specifications recommended operating conditions (agnd=dgnd=0 v, all voltages with respect to ground.) absolute maximum ratings (agnd = dgnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. typical analog input/out put performance will slightly degrade at va = 3.3 v. 2. the adc_sdout may not meet timing requirements in double-speed mode. 3. any pin except supplies. transien t currents of up to 100 ma on the analog input pins will not cause scr latch-up. 4. the maximum over/under voltage is limited by the input current. parameters symbol min max units dc power supply analog (note 1) va 3.14 5.25 v digital vd 3.14 3.47 v serial audio interface (note 2) vls 1.71 5.25 v control port inte rface vlc 1.71 5.25 v ambient temperature commercial -cmz automotive -dmz t a -40 -40 +85 +105 ? c ? c parameters symb ol min max units dc power supply analog digital serial port interface control port interface va vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 v v v v input current (note 3) i in - 1 0m a analog input voltage (note 4) v in agnd-0.7 va+0.7 v digital input voltage serial port interface (note 4) control port interface v ind-s v ind-c -0.3 -0.3 vls+ 0.4 vlc+ 0.4 v v ambient operating temperature (power applied) t a -50 +125 c storage temperature t stg -65 +150 c
14 ds685f3 cs42435 analog input characteristics (commercial) (test conditions (unless otherwise specified): va = 5 v, vd = vls = vlc = 3.3 v, and ta = 25c. full-scale input sine wave: 1 khz through the active input filter in figure 20 on page 48 and figure 20 on page 48 ; measurement bandwidth is 10 hz to 20 khz.) differential single-ended parameter min typ max min typ max unit fs=48 khz, 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 99 96 - 105 102 99 - - - 96 93 102 99 96 - - - db db db total harmonic distortion + noise -1 db (note 5) -20 db -60 db 40 khz bandwidth -1 db - - - - -98 -82 -42 -90 -92 - - - - - - - -95 -79 -39 -90 -89 - - - db db db db adc1-2 interchannel isolation - 90 - - 90 - db dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - 100 - - 100 - ppm/c analog input full-scale input voltage 1.06*va 1.12*va 1.18*va 0.53*va 0.56*va 0.59*va vpp differential input impedance (note 6) 23 29 32 - - - k ? single-ended input impedance (note 7) ---232932k ? common mode rejection ratio (cmrr) - 82 - - - - db
ds685f3 15 cs42435 analog input characteri stics (automotive) (test conditions (unless otherwise specified): va = 5 v5%, vd = vls = vlc = 3.3 v5% and ta = -40 ? to +85 ? c. full-scale input sine wave: 1 khz through the active input filter in figure 20 on page 48 and figure 19 on page 48 ; measurement bandwidth is 10 hz to 20 khz.) notes: 5. referred to the typical full-scale voltage. 6. measured between ainx+ and ainx-. 7. measured between ainxx and agnd. 8. the input impedance scales inversely proportionate to the sample rate of the adc modulator. differential single-ended parameter min typ max min typ max unit fs=48 khz, 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 97 94 - 105 102 99 - - - 94 91 - 102 99 96 - - - db db db total harmonic distortion + noise -1 db (note 5) -20 db -60 db 40 khz bandwidth -1 db - - - - -98 -82 -42 -87 -90 - - - - - - - -95 -79 -39 -87 -87 - - - db db db db adc1-2 interchannel isolation - 90 - - 90 - db dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - 100 - - 100 - ppm/c analog input full-scale input voltage 1.04*va 1.12*va 1.20*va 0.52*va 0.56*va 0.60*va vpp differential input impedance (note 6 & 8) 23 29 32 - - - k ? single-ended input impedance (note 7 & 8) - - - 23 29 32 k ? common mode rejection ratio (cmrr) -82----db
16 ds685f3 cs42435 adc digital filter characteristics notes: 9. filter response is guaranteed by design. 10. response is clock-dependent and will scale with fs. note that the response plots ( figures 25 to 32 ) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. parameter (notes 9, 10) min typ max unit single-speed mode (note 10) passband (frequency response) to -0.1 db corner 0 - 0.4896 fs passband ripple - - 0.08 db stopband 0.5688 - - fs stopband attenuation 70 - - db total group delay - 12/fs - s double-speed mode (note 10) passband (frequency response) to -0.1 db corner 0 - 0.4896 fs passband ripple - - 0.16 db stopband 0.5604 - - fs stopband attenuation 69 - - db total group delay - 9/fs - s high-pass filter characteristics frequency response -3.0 db -0.13 db -1 20 - - hz hz phase deviation @ 20 hz - 10 - deg passband ripple - - 0 db filter settling time - 10 5 /fs 0 s
ds685f3 17 cs42435 analog output character istics (commercial) (test conditions (unless otherwise specified): va = 5 v, vd = vls = vlc = 3.3 v, and ta = 25 c. full-scale 997 hz output sine wave (see note 12 ) into passive filter in figure 25 on page 51 and active filter in figure 25 on page 51 ; measurement bandwidth is 10 hz to 20 khz.) parameter differential min typ max single-ended min typ max unit fs = 48 khz, 96 khz, 192 khz dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 102 99 - - 108 105 99 96 - - - - 99 96 - - 105 102 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -98 -85 -45 -93 -76 -36 -92 - - - - - - - - - - -95 -82 -42 -90 -73 -33 -89 - - - - - db db db db db db interchannel isolation (1 khz) - 100 - - 100 - db analog output full-scale output 1.235?va 1.300?va 1.3 65?va 0.618?va 0.650?va 0.683?va vpp interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/c output impedance - 100 - - 100 - ? dc current draw from an aout pin (note 11) --10--10 ? a ac-load resistance (r l ) (note 13) 3--3--k ? load capacitance (c l ) (note 13) - - 100 - - 100 pf
18 ds685f3 cs42435 analog output charact eristics (automotive) (test conditions (unless otherwise specified): va = 5 v 5%, vd = vls = vlc = 3.3 v5% and ta = -40 to +85c. full-scale 997 hz output sine wave (see note 12 ) in figure 25 on page 51 and figure 25 on page 51 ; measure- ment bandwidth is 10 hz to 20 khz.) notes: 11. guaranteed by design. the dc current draw repres ents the allowed current draw from the aout pin due to typical leakage through the electrolytic dc-blocking capacitors. 12. one-half lsb of triangular pdf dither is added to data. 13. guaranteed by design. see figure 3 . r l and c l reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. in this circuit to- pology, c l will effectively move the dominan t pole of the two-pole amp in the output sta ge. increasing this value beyond the recommended 100 pf can cause the internal op-amp to become unstable. see ?external filters? on page 48 for a recommended output filter. parameter differential min typ max single-ended min typ max unit fs = 48 khz, 96 khz, 192 khz dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 100 97 - - 108 105 99 96 - - - - 97 94 - - 105 102 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -98 -85 -45 -93 -76 -36 -90 - - - - - - - - - - - -95 -82 -42 -90 -73 -33 -87 - - - - - db db db db db db interchannel isolation (1 khz) - 100 - - 100 - db analog output full-scale output 1.210?va 1.300?va 1. 392?va 0.605?va 0.650?va 0.696?va vpp interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/c output impedance - 100 - - 100 - ? dc current draw from an aout pin (note 11) - - 10 - - 10 ? a ac-load resistance (r l ) (note 13) 3--3--k ? load capacitance (c l ) (note 13) - - 100 - - 100 pf
ds685f3 19 cs42435 100 50 75 25 2.5 51 01 5 safe operating region capacitive load -- c (pf) l resistive load -- r (k ? ) l 125 3 20 aoutxx 3.3 f analog output c l + r l dac1-4 agnd figure 3. output test circuit for ma ximum load figure 4. maximum loading
20 ds685f3 cs42435 combined dac interp olation & on-chip ana log filter response notes: 14. response is clock-dependent and will scale with fs. note that the response plots ( figures 33 to 44 ) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 15. single- and double-speed mode measurement bandwidth is from stopband to 3 fs. quad-speed mode measurement bandwidth is from stopband to 1.34 fs. 16. de-emphasis is only available in single-speed mode. parameter (notes 9, 14) min typ max unit single-speed mode passband (frequency response) to -0.05 db corner to -3 db corner 0 0 - - 0.4780 0.4996 fs fs frequency response 10 hz to 20 khz -0.2 - +0.08 db stopband 0.5465 - - fs stopband attenuation (note 15) 50 - - db group delay - 10/fs - s de-emphasis error (note 16) fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - +1.5/+0 +0.05/-0.25 -0.2/-0.4 db db db double-speed mode passband (frequency response) to -0.1 db corner to -3 db corner 0 0 - - 0.4650 0.4982 fs fs frequency response 10 hz to 20 khz -0.2 - +0.7 db stopband 0.5770 - - fs stopband attenuation (note 15) 55 - - db group delay - 5/fs - s quad-speed mode passband (frequency response) to -0.1 db corner to -3 db corner 0 0 - - 0.397 0.476 fs fs frequency response 10 hz to 20 khz -0.2 - +0.05 db stopband 0.7 - - fs stopband attenuation (note 15) 51 - - db group delay - 2.5/fs - s
ds685f3 21 cs42435 switching specificat ions - adc/dac port (inputs: logic 0 = dgnd, logic 1 = vls, adc_sdout c load = 15 pf.) notes: 17. after powering up the cs42435, rst should be held low after the power supplies and clocks are settled. 18. see table 5 on page 41 for suggested mclk frequencies. 19. vls is limited to nominal 2.5 v to 5.0 v operation only. 20. adc does not meet timing spec ification for quad-speed mode. parameters symbol min max units slave mode rst pin low pulse width (note 17) 1 -ms mclk frequency 0.512 50 mhz mclk duty cycle (note 18) 45 55 % input sample rate (fs pin) single-speed mode double-speed mode (note 19) quad-speed mode (note 20) f s f s f s 4 50 100 50 100 200 khz khz khz sclk duty cycle 45 55 % sclk high time t sckh 8-n s sclk low time t sckl 8-n s fs rising edge to sclk rising edge t fss 5-n s sclk rising edge to fs falling edge t fsh 16 - ns dac_sdin setup time be fore sclk rising edge t ds 3-n s dac_sdin hold time after sclk rising edge t dh 5-n s dac_sdin hold time after sclk rising edge t dh1 5-n s adc_sdout hold time af ter sclk rising edge t dh2 10 - ns adc_sdout valid before sclk rising edge t dval 15 - ns adc_sdout dac_sdin t ds sclk (input) fs (input) msb t dh1 t sckh t sckl t dval msb-1 msb msb-1 t fsh t fss t dh2 figure 5. tdm serial audio interface timing
22 ds685f3 cs42435 switching characte ristics - aux port (inputs: logic 0 = dgnd, logic 1 = vls.) parameters symbol min max units master mode output sample rate (aux _lrck) all speed modes f s -f sk h z aux_sclk frequency - 64 fs khz aux_sclk duty cycle 45 55 % aux_lrck edge to sclk rising edge t lcks -5n s aux_sdin setup time before sclk rising edge t ds 3-n s aux_sdin hold time after sclk rising edge t dh 5-n s aux_sdin aux_sclk aux_lrck t sckh t sckl t lcks t ds msb t dh msb-1 figure 6. serial audio interface slave mode timing
ds685f3 23 cs42435 switching specifications - control port - i2c mode (vlc = 1.8 v - 5.0 v, vls = vd = 3.3 v, va = 5. 0 v; inputs: logic 0 = dgnd, logic 1 = vlc, sda c l =30pf) notes: 21. data must be held for sufficient time to bridge the transition time, t fc , of scl. 22. guaranteed by design. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 21) t hdd 0- s sda setup time to scl rising t sud 250 - ns rise time of scl and sda (note 22) t rc -1 s fall time scl and sda (note 22) t fc -3 0 0n s setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t low t hdd t high t sud stop start sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack figure 7. control port timing - i2c format
24 ds685f3 cs42435 switching specificat ions - control po rt - spi format (vlc = 1.8 v - 5.0 v, vls = vd = 3.3 v, va = 5.0 v; inputs: logic 0 = dgnd, logic 1 = vlc, cdout c l =30pf) notes: 23. data must be held for sufficient time to bridge the transition time of cclk. 24. for f sck <1 mhz. parameter symbol min max units cclk clock frequency f sck 06 . 0m h z rst rising edge to cs falling t srs 20 - ns cs falling to cclk edge t css 20 - ns cs high time between transmissions t csh 1.0 - ? s cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 23) t dh 15 - ns cclk falling to cdout stable t pd -5 0n s rise time of cdout t r1 -2 5n s fall time of cdout t f1 -2 5n s rise time of cclk and cdin (note 24) t r2 - 100 ns fall time of cclk and cdin (note 24) t f2 - 100 ns cs cclk cdin cdout rst t srs t scl t sch t css t r2 t f2 t csh t dsu t dh msb msb t pd figure 8. control port timing - spi format
ds685f3 25 cs42435 dc electrical characteristics (agnd = 0 v; all voltages with respect to ground.) notes: 25. normal operation is defined as rst = hi with a 997 hz, 0 dbfs input to the dac and aux port, and a 1 khz, -1 db analog input to the adc port sampled at the highest f s for each speed mode. dac outputs are open, unless otherwise specified. 26. i dt measured with no external loading on pin (sda). 27. valid with the recommended capa citor values on filt + and vq. increasing the capacitance will also increase the psrr. 28. power-down mode is defined as rst = lo with all clocks and data lines held static and no analog input. 29. guaranteed by design. the dc current draw represents the allowed current draw from the vq pin due to typical leakage through the electrolytic de-coupling capacitors. digital interface specifications & characteristics notes: 30. see ?digital i/o pin characteristics? on page 8 for serial and control port power rails. parameters symbol min typ max units normal operation (note 25) power supply curr ent va = 5.0 v vls = vlc = vd = 3.3 v (note 26) i a i dt - - 80 60.6 - - ma ma power dissipation vls = vlc = vd = 3.3 v,5 v - 600 850 mw power supply rejection ratio 1 khz (note 27) 60 hz psrr - - 60 40 - - db db power-down mode (note 28) power dissipation vls = vlc = vd = 3.3 v,va = 5 v - 1.25 - mw vq characteristics nominal voltage output impedance dc current source/sink (note 29) - - - 0.5?va 23 - - - 10 v k? ? a filt+ nominal voltage - va - v parameters (note 30) symbol min typ max units high-level output voltage at i o =2 ma serial port control port v oh vls-1.0 vlc-1.0 - - - - v v low-level output voltage at i o =2 ma serial port control port v ol - - - - 0.4 0.4 v v high-level input voltage serial port control port v ih 0.7xvls 0.7xvlc - - - - v v low-level input voltage serial port control port v il - - - - 0.2xvls 0.2xvlc v v leakage current i in --10 ? a input capacitance (note 22) - - 10 pf
26 ds685f3 cs42435 5. applications 5.1 overview the cs42435 is a highly integrated mixed signal 24-bi t audio codec comprised of 4 analog-to-digital con- verters (adc) implemented using multi-bit delta-sigma techniques and 8 digital-to-analog converters (dac) also implemented using multi-bit delta-sigma techniques. other functions integrated within the codec include indep endent digital volume controls for each dac, dig- ital de-emphasis filters for the dac, digital volume control with gain on each adc channel, adc high-pass filters, and an on-chi p voltage reference. the serial audio interface ports allow up to 8 dac c hannels and 6 adc channels in a time-division multi- plexed (tdm) interface format. the cs 42435 features an auxiliary port used to accommodate an additional two channels of pcm data on the adc_sdout data line in the tdm digital interface format. see ?aux port digital interface formats? on page 32 for details. the cs42435 operates in one of three oversampling modes based on the input sample rate. mode selection is determined automatically based on the mclk frequ ency setting. single-speed mode (ssm) supports in- put sample rates up to 50 khz and uses a 128x oversampling ratio. double-speed mode (dsm) supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad-speed mode (qsm) sup- ports input sample rates up to 200 khz and uses an oversampling ratio of 32x ( note: qsm for the adc is only supported in the i2s, left-justified, right-justifi ed interface formats. qsm is not supported for the adc in the tdm interface format). note: qsm is only available in software mode (see ?system clocking? on page 31 for details). all functions can be configured through software via a serial control port operable in spi mode or in i2c mode. a hardware, stand-alone mode is also availa ble, allowing configuratio n of the codec on a more limited basis. see table 2 for the def ault configuration in hardware mode. figure 1 on page 11 and figure 2 on page 12 show the recommended connections for the cs42435 in soft- ware and hardware mo de, respectively. see ?register description? on page 39 for the default register set- tings and options in software mode. hardware mode feature summary function default configuration hardware control note power down adc all adc?s are enabled - - power down dac all dac?s are enabled - - power down device device is powered up - - mclk frequency select selectable between 256fs and 512fs ?mfreq? pin 3 see section 5.4 freeze control n/a - - aux serial port interface format left-justified - - adc1 high pass filter freeze high pass filter is always enabled -- dac de-emphasis no de-emphasis applied - - adc1 single-ended mode disabled - - dac volume control/mute/invert all dac volume = 0 db, un- muted, not inverted -- adc volume control all adc volume = 0 db - - dac soft ramp/zero cross immediate change - - adc soft ramp/zero cross immediate change - - table 2. hardware co nfigurable settings
ds685f3 27 cs42435 5.2 analog inputs 5.2.1 line-level inputs ainx+ and ainx- are the line-level di fferential analog inputs internally biased to vq, approximately va/2. figure 9 on page 27 shows the full-scale analog input leve ls. the cs42435 also accommodates single- ended signals on all inputs, ain1-ain4. see ?adc input filter? on page 48 for the recommended input filters. 5.2.1.1 hardware mode ain volume control and adc overflow status are not accessible in hardware mode. 5.2.1.2 software mode for single-ended operation on adc1-adc2 (ain1 to ain4), the adcx_single bit in the register ?adc control & dac de-emphasis (address 05h)? on page 42 must be set appropriately (see figure 20 on page 48 for required external components). the gain/attenuation of the signal can be adjusted for each ainx independently through the ?ainx volume control (address 11h-14h)? on page 45 . the adc output data is in 2?s complement binary format. for in- puts above positive full scale or below negative full scale, the adc will output 7fffffh or 800000h, re- spectively, and cause the adc ov erflow bit in the register ?status (address 19h) (read only)? on page 46 to be set to a ?1?. 5.2.2 high-pass filter and dc offset calibration the high-pass filter continuously su btracts a measure of the dc offset from the output of the decimation filter. if the high-pass filter is disabled during norm al operation, the current va lue of the dc offset for the dac auto-mute enabled - - status interrupt n/a - - hardware mode feature summary function default configuration hardware control note table 2. hardware configurable settings (continued) full-scale differential input level = (ainx+) - (ainx-) = 5.6 v pp = 1.98 v rms ainx+ ainx- 3.9 v 2.5 v 1.1 v 5.0 v 3.9 v 2.5 v 1.1 v va figure 9. full-scale input
28 ds685f3 cs42435 corresponding channel is fr ozen and this dc offset will continue to be subtracted from the conversion re- sult. this feature makes it possible to perform a system dc offset calibration by: 1. running the cs42435 with the high-pass filter enabled until the filter settles. see the digital filter characteristics for filter settling time. 2. disabling the high-pass filter and freezing the stored dc offset. 5.2.2.1 hardware mode the high pass filters for adc1 and adc2 are permanently enabled in hardware mode. software mode. the high-pass filter for adc1/adc2 can be enabled an d disabled. the high-pass filters are controlled us- ing the hpf_freeze bit in the register ?adc control & dac de-emphasis (address 05h)? on page 42 . 5.3 analog outputs 5.3.1 initialization the initialization and po wer-down sequence flow chart is shown in figure 10 on page 29 . the cs42438 enters a power-down state upon initial power-up. th e interpolation and decima tion filters, delta-sigma modulators and control port registers are reset. the in ternal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and switched -capacitor low-pass filters are powered down. the device remains in the power-down state until the rs t pin is brought high. the control port is acces- sible once rst is high, and the desired register se ttings can be loaded per the interface descriptions in the ?control port description and timing? on page 33 . in hardware mode oper ation, the hardware mode pins must be set up before rst is brought high. all features will default to t he hardware mo de defaults as listed in table 2 . vq will quickly charge to va/2 upon init ial power up. once mclk is valid and the pdn bit is set to ?0?b, the internal voltage reference, filt+, will ramp up to approximately va. power is app lied to the d/a con- verters and switched-capacitor filter s, and the analog outputs are clam ped to the quiescent voltage, vq. once lrck is valid, mclk occurrences are counte d over one lrck period to determine the mclk/lrck frequency ratio. after an approximate 2000 sample period delay, normal operation begins. 5.3.2 line-level outputs and filtering the cs42435 contains on-chip buffer amplifiers capable of producing line-level differential as well as sin- gle-ended outputs on aout1-aout8. these amplifiers are biased to a quiescent dc level of approxi- mately vq. the delta-sigma conversion process produces high- frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. the remaining out-of-band noise can be attenuated using an off-chip low-pass filter. see ?dac output filter? on page 50 for recommended output filter. the ac tive filter configuration accounts for the normally differing ac loads on the aoutx+ and aoutx- differential output pins. also shown is a passive filter configuration which minimizes costs and the number of components. figure 11 shows the full-scale analog output levels. all out puts are internally biased to vq, approximately va/2.
ds685f3 29 cs42435 no power 1. vq = ? 2. aout bias = ? 3. no audio signal generated. control port accessed control port access detected? valid mclk applied? valid mclk applied? no pdn bit = '1'b? sub-clocks applied 1. lrck valid. 2. sclk valid. 3. audio samples processed. valid mclk/lrck ratio? no yes yes no yes no yes no yes yes no normal operation 1. vq = va/2. 2. aout bias = va/2. 3. audio signal generated per register settings. analog output freeze 1. vq = va/2. 2. aout bias = va/2 + last audio sample. 3. no audio signal generated. analog output mute 1. vq = va/2. 2. aout bias = va/2. 3. no audio signal generated. error: mclk/lrck ratio change error: mclk removed rst = low error: power removed pdn bit set to '1'b software mode registers setup to desired settings. hardware mode h/w pins setup to desired settings. rst = low? 2000 lrck delay power-up 1. vq = va/2. 2. aout bias = vq. power-down 1. vq = va/2. 2. aout bias = hi-z. 3. no audio signal generated. 4. control port registers retain settings. power-down (power applied) 1. vq = va/2. 2. aout = hi-z. 3. no audio signal generated. 4. control port registers reset to default. figure 10. audio output initialization flow chart
30 ds685f3 cs42435 5.3.3 digital volume control 5.3.3.1 hardware mode dac volume control and mute are not accessible in hardware mode. 5.3.3.2 software mode each dac?s output level is contro lled via the volume control registers operating over the range of 0 to -127.5 db attenuation with 0.5 db resolution. see ?aoutx volume control (addresses 08h- 0fh)? on page 45 . volume control changes are programmable to ramp in increments of 0.125 db at the rate con- trolled by the szc[1:0] bits in the digital volume cont rol register. see ?transition contro l (address 06h)? on page 43 . each output can be independently muted via mute control bits in the register ?dac channel mute (ad- dress 07h)? on page 44 . when enabled, each aoutx_mute bit attenuates the corresponding dac to its maximum value (-127.5 db). when the aoutx_mute bit is disabled, the corresponding dac returns to the attenuation level set in the volume control register. the attenuation is ramped up and down at the rate specified by the szc[1:0] bits. 5.3.4 de-emphasis filter the cs42435 includes on-chip digital de-emphasis optimi zed for a sample rate of 44.1 khz. the filter re- sponse is shown in figure 12 . the de-emphasis feature is included to accommodate audio recordings that utilize 50/15 ? s pre-emphasis equalization as a means of noise reduction. de-emphasis is only available in single-speed mode. please see ?dac de-emphasis control (dac_dem)? on page 42 for de-emphasis control. aoutx+ aoutx- full-scale differential output level = (aoutx+) - (aoutx-) = 6.5 v pp = 2.3 v rms 4.125 v 2.5 v 0.875 v 5.0 v 4.125 v 2.5 v 0.875 v va figure 11. full-scale output
ds685f3 31 cs42435 5.4 system clocking the codec serial audio interface ports operate as a slave and accept externally generated clocks. the codec requires external generation of the master clock (mclk). the frequency of this clock must be an integer multiple of, and synchronous with, the system sample rate, fs. 5.4.1 hardware mode the allowable ratios include 256fs and 512fs in single-speed mode and 256fs in double-speed mode. the frequency of mclk must be spec ified using the mfreq (pin 3). see table 3 for the required frequen- cy range. 5.4.2 software mode the frequency range of mclk must be spec ified using the mfreq bits in register ?mclk frequency (mfreq[2:0])? on page 41 . 5.5 codec digital interface the adc and dac serial ports operate as a slave and support the tdm digital interface formats with varying bit depths from 16 to 32 as shown in figure 13 on page 32 . data is clocked out of the adc on the falling edge of sclk and clocked into the dac on the rising edge. tdm is the only interface supported in hardware and software mode. 5.5.1 tdm tdm data is received most significant bit (msb) firs t, on the second rising edge of the sclk occurring after an fs rising edge. all data is valid on the rising ed ge of sclk. the ain1 msb is transmitted early, but is guaranteed va lid for a specified time after sclk rises. all other bits are tran smitted on the falling edge of sclk. each time slot is 32 bits wide, with th e valid data sample left just ified within the time slot. valid data lengths ar e 16, 18, 20, or 24. sclk must operate at 256fs. fs identifies the start of a new frame and is equal to the sample rate, fs. ratio (xfs) mfreq description ssm dsm qsm 0 1.5360 mhz to 12.8000 mhz 256 n/a n/a 1 2.0480 mhz to 25.6000 mhz 512 256 n/a table 3. mclk frequency settings gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183khz 10.61khz figure 12. de-emphasis curve
32 ds685f3 cs42435 fs is sampled as valid on the rising sclk edge precedi ng the most significant bit of the first data sample and must be held valid for at least 1 sclk period. note: the adc does not meet the timing requirements for proper operation in quad-speed mode. 5.5.2 i/o channel allocation 5.6 aux port digita l interface formats these serial data lines are used when supporting the tdm mode of operation with an external adc or s/pdif receiver attached. the aux serial port operate s only as a clock master. the aux_sclk will operate at 64xfs, where fs is equal to the adc sample rate (fs on the tdm interface). if the aux_sdin signal is not being used, it should be tied to agnd via a pull-down resistor. 5.6.1 hardware mode the aux port will only op erate in the left-justified digital interface fo rmat and supports bit depths ranging from 16 to 24 bits (see figure 17 on page 34 for timing relationship between aux_lrck and aux_sclk). 5.6.2 software mode the aux port will operate in either th e left-justified or i2s digital interf ace format with bit depths ranging from 16 to 24 bits. settings for the aux port are made through the register ?miscellaneous control (ad- dress 04h)? on page 41 . 5.6.3 i2s digital input/output interface format analog output/input channel allocation from/to digital i/o dac_sdin tdm aout 1,2,3,4,5,6,7,8 adc_sdout tdm ain 1,2,3,4 (2 additi onal channels from aux_sdin) table 4. serial audio in terface channel allocations sclk fs 256 clks bit or word wide aout6 lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb dac_sdin aout1 aout4 aout2 aout5 aout3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks aout8 lsb msb lsb msb aou7 32 clks 32 clks msb lsb - lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb adc_sdout ain1 ain4 ain2 - ain3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks aux2 lsb msb lsb msb aux1 32 clks 32 clks msb figure 13. tdm serial audio format aux_lrck aux_sclk msb lsb msb lsb aux1 left channel right channel aux_sdin aux2 msb figure 14. aux i2s format
ds685f3 33 cs42435 5.6.4 left-justified 5.7 control port description and timing the control port is used to access the registers, in software mode, allowing the cs42435 to be configured for the desired operational modes and formats. the opera tion of the control port may be completely asyn- chronous with respect to the audio sample rates. howe ver, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port has two modes: spi and i2c, with the cs42435 acting as a slave device. spi mode is se- lected if there is a high-to-low transition on the ad0/cs pin, after the rst pin has been brought high. i2c mode is selected by connecting the ad0/cs pin through a resistor to vlc or dgnd, thereby permanently selecting the desired ad0 bit address state. 5.7.1 spi mode in spi mode, cs is the cs42435 chip-select signal, cclk is the control port bit clock (input into the cs42435 from the microcontroller), cdin is the inpu t data line from the micr ocontroller, cdout is the output data line to the microcontroller. data is clocked in on the rising edge of cclk and out on the falling edge. figure 16 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and mu st be 1001111. the eighth bit is a read/write indi- cator (r/w ), which should be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the r egister that is to be updated. the ne xt eight bits are the data which will be placed into the register designated by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k ? resistor, if desired. there is a map auto-increment capab ility, enabled by the incr bit in the map register. if incr is a zero, the map will stay constant for successive read or writ es. if incr is set to a 1, the map will auto-increment after each byte is read or wr itten, allowing block reads or wr ites of successive registers. to read a register, the map has to be set to the correct address by executing a partial write cycle which finishes (cs high) immediately afte r the map byte. the map auto-incre ment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). if the map auto-i ncrement bit is set to 1, the data for successive registers will appear consecutively. aux_lrck aux_sclk msb lsb msb lsb aux1 left channel right channel aux_sdin aux2 msb figure 15. aux left-justified format
34 ds685f3 cs42435 5.7.2 i2c mode in i2c mode, sda is a bidirectional da ta line. data is clocke d into and out of the pa rt by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two least-si gnificant bits of the chip address and should be connected through a resistor to vlc or dgnd as de sired. the state of the pins is sensed while the cs42435 is being reset. the signal timings for a read and write cycle are shown in figure 17 and figure 18 . a start condition is defined as a falling transition of sda while the clock is high. a stop condition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the cs42435 after a start condition consists of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper 5 bits of the 7-bit address field are fixed at 10010. to communicate with a cs42435, the chip address field, which is the first byte sent to the cs42435, should match 10010 followed by the settings of the ad1 and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address poin ter (map) which selects the register to be read or written. if the op- eration is a read, the cont ents of the register pointed to by the map will be output. setting the auto-incre- ment bit in map allows successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the cs42435 after each input byte is read, and is input to the cs42435 from the microcontroller after each transmitted byte. map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 1001111 1001111 map = memory address pointer, 8 bits, msb first high impedance figure 16. control port timing in spi mode 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 ad1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 17. control port timing, i2c write
ds685f3 35 cs42435 since the read operation c annot set the map, an aborted write operation is used as a preamble. as shown in figure 18 , the write operation is aborted after the ackno wledge for the map byte by sending a stop con- dition. the following pseudocode illu strates an aborted wr ite operation followed by a read operation. send start condition. send 10010xx0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 10010xx1(chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto-increment bit in the map allows succes sive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. 5.8 recommended power-up sequence 5.8.1 hardware mode 1. hold rst low until the power supply, clocks and hardware control pins are stable. in this state, the control port is reset to its defa ult settings and vq will remain low. 2. bring rst high. the device will initially be in a low power state with vq low. 3. the device will initiate the hard ware mode power up sequence. all features will default to the hardware mode defaults as listed in table 2 on page 26 according to the hardware mode control pins. vq will quick-charge to approximately va/2 and the analog output bias will clamp to vq. 4. following approximately 2000 sample periods, the device is initialized and ready for normal operation. note: during the hardware mode power-up sequence, th ere must be no transitions on any of the hard- ware control pins. scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 ad1 ad0 0 sda 1 0 0 1 0 ad1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 18. control port timing, i2c read
36 ds685f3 cs42435 5.8.2 software mode 1. hold rst low until the power supply and clocks are stable. in this state, the control port is reset to its default settings and vq will remain low. 2. bring rst high. the device will initially be in a low power state with vq low. all featur es will default as described in the ?register quick reference? on page 37 . 3. perform a write operation to the power control register ( ?power control (address 02h)? on page 40 ) to set bit 0 to a ?1?b. this will place the device in a power down state. 4. load the desired register settings wh ile keeping the pdn bit set to ?1?b. 5. mute all dacs. muting the dacs suppresses any nois e associated with the code c's first initialization after power is applied. 6. set the pdn bit in the power control register to ?0 ?b.following approximately 2000 lrck cycles, the de- vice is initialized and ready for normal operation. 7. after the codec is initialized, wait ~90 lrck cycles (~1.9 ms @48 khz) and then unmute the dacs. 8. normal operation begins. 5.9 reset and power-up it is recommended that reset be activated if the anal og or digital supplies drop below the recommended op- erating condition to prevent power-glitch-related issues. the delta-sigma modulators settle in a matter of mi croseconds after the analog section is powered, either through the application of power or by setting the rst pin high. however, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the filt+ pin. a time delay of approximately 400 ms is requ ired after applying power to the devi ce or after exiting a reset state. during this voltage reference ramp delay, all serial ports and dac outputs will be auto matically muted. 5.10 power supply, gr ounding, and pcb layout as with any high-resolution converter, the cs42435 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figure 1 and figure 2 show the recommend- ed power arrangements, with va connected to clean supplies. vd, which powers the digital circuitry, may be run from the system logic supply. extensive use of power and ground planes, ground plane fill in un used areas and surf ace mount decoupling capacitors are recommended. decoupling capacitors shoul d be as near to the pins of the cs42435 as pos- sible. the low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the cs42435 to minimize inductance effects. all signals, especially clocks, should be kept away from the filt+, vq pins in order to avoid unwanted coupling into the modulators. the filt+ and vq decoupling capacitors, particularly the 0.1 f, must be positioned to minimize the electrical path from filt+ and agnd. the cdb42438 evaluation board demo nstrates the optimum layout and power supply arrangements. for optimal heat dissipation from the package, it is recommended that the area directly under the part be filled with copper and tied to the ground plane. the use of vias connecting the topside ground to the back- side ground is also recommended.
ds685f3 37 cs42435 6. register qu ick reference software mode register defaults are as shown. note : the default value in all ?reserved? registers must be pre- served. addr function 76543210 01h id chip_id3 chip_id2 chip_id1 chip_id0 rev_id3 rev_id2 rev_id1 rev_id0 p39 default 0 0 0 1 0 0 0 1 02h power con- trol reserved pdn_adc2 pdn_adc1 pdn_dac4 pdn_dac3 pdn_dac2 pdn_dac1 pdn p40 default 0 0 0 0 0 0 0 0 03h functional mode reserved reserved reserved reserved mfreq2 mfreq1 mfreq0 reserved p41 default 1 1 1 1 0 0 0 0 04h misc control freeze aux_dif reserved reserved reserved reserved reserved reserved p41 default 0 0 1 1 0 1 10 05h adc control (w/dac_dem) adc1-2_hpf freeze reserved dac_dem adc1 single adc2 single reserved reserved reserved p42 default 0 0 0 0 0 0 0 0 06h transition control dac_sng vol dac_szc1 dac_szc0 amute mute adc_sp adc_sng vol adc_szc1 adc_szc0 p43 default 0 0 0 1 0 0 0 0 07h channel mute aout8 mute aout7 mute aout6 mute aout5 mute aout4 mute aout3 mute aout2 mute aout1 mute p44 default 0 0 0 0 0 0 0 0 08h vol. control aout1 aout1 vol7 aout1 vol6 aout1 vol5 aout1 vol4 aout1 vol3 aout1 vol2 aout1 vol1 aout1 vol0 p45 default 0 0 0 0 0 0 0 0 09h vol. control aout2 aout2 vol7 aout2 vol6 aout2 vol5 aout2 vol4 aout2 vol3 aout2 vol2 aout2 vol1 aout2 vol0 p45 default 0 0 0 0 0 0 0 0 0ah vol. control aout3 aout3 vol7 aout3 vol6 aout3 vol5 aout3 vol4 aout3 vol3 aout3 vol2 aout3 vol1 aout3 vol0 p45 default 0 0 0 0 0 0 0 0 0bh vol. control aout4 aout4 vol7 ao ut4 vol6 aout4 vol5 aout4 vol4 aout4 vol3 aout4 vol2 aout4 vol1 aout4 vol0 p45 default 0 0 0 0 0 0 0 0 0ch vol. control aout5 aout5 vol7 aout5 vol6 aout5 vol5 aout5 vol4 aout5 vol3 aout5 vol2 aout5 vol1 aout5 vol0 p45 default 0 0 0 0 0 0 0 0 0dh vol. control aout6 aout6 vol7 aout6 vol6 aout6 vol5 aout6 vol4 aout6 vol3 aout6 vol2 aout6 vol1 aout6 vol0 p45 default 0 0 0 0 0 0 0 0 0eh vol. control aout7 aout7 vol7 aout7 vol6 aout7 vol5 aout7 vol4 aout7 vol3 aout7 vol2 aout7 vol1 aout7 vol0 p45 default 0 0 0 0 0 0 0 0 0fh vol. control aout8 aout8 vol7 aout8 vol6 aout8 vol5 aout8 vol4 aout8 vol3 aout8 vol2 aout8 vol1 aout8 vol0 p45 default 0 0 0 0 0 0 0 0 10h dac chan- nel invert inv_aout8 inv_aout7 inv_aout6 inv_aout5 inv_aout4 inv_aout3 inv_aout2 inv_aout1 p45 default 0 0 0 0 0 0 0 0
38 ds685f3 cs42435 11h vol. control ain1 ain1 vol7 ain1 vol6 ain1 vol5 ain1 vol4 ain1 vol3 ain1 vol2 ain1 vol1 ain1 vol0 p45 default 0 0 0 0 0 0 0 0 12h vol. control ain2 ain2 vol7 ain2 vol6 ain2 vol5 ain2 vol4 ain2 vol3 ain2 vol2 ain2 vol1 ain2 vol0 p45 default 0 0 0 0 0 0 0 0 13h vol. control ain3 ain3 vol7 ain3 vol6 ain3 vol5 ain3 vol4 ain3 vol3 ain3 vol2 ain3 vol1 ain3 vol0 p45 default 0 0 0 0 0 0 0 0 14h vol. control ain4 ain4 vol7 ain4 vol6 ain4 vol5 ain4 vol4 ain4 vol3 ain4 vol2 ain4 vol1 ain4 vol0 p45 default 0 0 0 0 0 0 0 0 15h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 16h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 17h adc chan- nel invert reserved reserved reserved reserved inv_a4 inv_a3 inv_a2 inv_a1 p45 default 0 0 0 0 0 0 0 0 18h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 19h status reserved reserved reserved clk error reserved adc2 ovfl adc1 ovfl p46 default 0 0 0 x x x x x 1ah status mask reserved reserved reserv ed reserved clk error_m reserved adc2_ovf l_m adc1_ovfl _m p4 7 default 0 0 0 0 0 0 0 0 addr function 76543210
ds685f3 39 cs42435 7. register description all registers are read/write except for the i.d. and revision register and in terrupt status register which are read only. see the following bit-definition tabl es for bit assignment information. the default state of each bit after a power- up sequence or reset is liste d in each bit description. 7.1 memory address pointer (map) not a register 7.1.1 increment (incr) default = 1 function: memory address pointer auto increment control 0 - map is not incremented automatically. 1 - internal map is automatically incremented after each read or write. 7.1.2 memory address pointer (map[6:0]) default = 0000001 function: memory address pointer (map). sets the register address that will be re ad or written by the control port. 7.2 chip i.d. and revision regist er (address 01h) (read only) 7.2.1 chip i.d. (chip_id[3:0]) default = 0001 function: i.d. code for the cs42435. permanently set to 0000. 7.2.2 chip revision (rev_id[3:0]) default = xxxx function: cs42435 revision level. revision a is coded as 0001. 76543210 incr map6 map5 map4 map3 map2 map1 map0 76543210 chip_id3 chip_id2 chip_id1 chip_i d0 rev_id3 rev_id2 rev_id1 rev_id0
40 ds685f3 cs42435 7.3 power control (address 02h) 7.3.1 power down adc pairs (pdn_adcx) default = 0 0 - disable 1 - enable function: when enabled, the re spective adc channel pair (adc1 - ain1/ain2; and adc2 - ain3/ain4) will remain in a reset state. 7.3.2 power down dac pairs (pdn_dacx) default = 0 0 - disable 1 - enable function: when enabled, the respective dac channel pair (dac1 - aout1/aout2; da c2 - aout3/aout4; dac3 - aout5/aout6; and dac4 - aout7/ aout8) will remain in a reset state. it is advised that any change of these bits be made while the dacs are muted or the power down bit (pdn) is enabled to eliminate the possibility of audible artifacts. 7.3.3 power down (pdn) default = 0 0 - disable 1 - enable function: the entire device will enter a low-powe r state when this function is enabled. the contents of the control registers are retained in this mode. 76543210 reserved pdn_adc2 pdn_adc1 pdn_da c4 pdn_dac3 pdn_dac2 pdn_dac1 pdn
ds685f3 41 cs42435 7.4 functional mode (address 03h) 7.4.1 mclk frequency (mfreq[2:0]) default = 000 function: sets the appropriate frequency for the supplied mc lk. for tdm operation, sclk must equal 256fs. mclk can be equal to or greater than sclk. 7.5 miscellaneous control (address 04h) 7.5.1 freeze controls (freeze) default = 0 function: this function will freeze the previous settings of, and allow modification s to be made to the channel mutes, the dac and adc volume control/chan nel invert registers without the changes taking effect until the freeze is disabled. to have multiple changes in these control port registers take effect simultaneously, enable the freeze bit, make all register changes, then disable the freeze bit. 7.5.2 auxiliary digital interface format (aux_dif) default = 0 0 - left justified 1 - i2s function: this bit selects the digital interf ace format used for the aux serial port. the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 16 - 17. 76543210 reserved reserved reserved reserved mfreq2 mfreq1 mfreq0 reserved ratio (xfs) mfreq2 mfreq1 mfreq0 de scription ssm dsm qsm 000 1.0290 mhz to 12.8000 mhz 256 n/a n/a 001 1.5360 mhz to 19.2000 mhz 384 n/a n/a 010 2.0480 mhz to 25.6000 mhz 512 256 n/a 011 3.0720 mhz to 38.4000 mhz 768 384 n/a 1xx 4.0960 mhz to 51.2000 mhz 1024 512 256 table 5. mclk frequency settings 76543210 freeze aux_dif reserved reserved reserved reserved reserved reserved
42 ds685f3 cs42435 7.6 adc control & dac de-e mphasis (address 05h) 7.6.1 adc1-2 high-pass filter freeze (adc1-2_hpf freeze) default = 0 function: when this bit is set, th e internal high-pass filter will be disabled for adc1 and adc2.the current dc offset value will be frozen and continue to be subtracted from the conversion result. see ?adc digital filter characteristics? on page 16 . 7.6.2 dac de-emphasis control (dac_dem) default = 0 0 - no de-emphasis 1 - de-emphasis enabl ed (auto-detect fs) function: enables the digital filter to maintain the standard 15 ? s/50? s digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 khz. de-emphasi s will not be enabl ed, regardless of this register setting, at any other sample rate. 7.6.3 adc1 single-ended mode (adc1 single) default = 0 0 - disabled; differential input to adc1 1 - enabled; single-ended input to adc1 function: when enabled, this bit allows the user to apply a si ngle-ended input to the positive terminal of adc1. a +6 db digital gain is automatically applied to the serial audio data of adc1. the negative leg must be driv- en to the common mode of the adc. see figure 20 on page 48 for a graphical description. 76543210 adc1-2_hpf freeze reserved dac_dem adc1 single adc2 single reserved reserved reserved
ds685f3 43 cs42435 7.6.4 adc2 single-ended mode (adc2 single) default = 0 0 - disabled; differential input to adc2 1 - enabled; single-ended input to adc2 function: when enabled, this bit allows the user to apply a si ngle-ended input to the positive terminal of adc2. a +6 db digital gain is automatically applied to the serial audio data of adc2. the negative leg must be driv- en to the common mode of the adc. see figure 20 on page 48 for a graphical description. 7.7 transition control (address 06h) 7.7.1 single volume contro l (dac_sngvol, adc_sngvol) default = 0 function: the individual channel volume levels are independently controlled by their respec tive volume control reg- isters when this function is disabled. when enabled , the volume on all channels is determined by the aout1 and ain1 volume control register and the other volume control registers are ignored. 7.7.2 soft ramp and zero cross c ontrol (adc_szc[1:0] , dac_szc[1:0]) default = 00 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: immediate change when immediate change is selected, all volume-level changes will take effect immediately in one step. zero cross zero cross enable dictates that signal level changes, either by gain changes, attenuation changes or mut- ing, will occur on a signal zero crossing to minimize audible artifacts. the re quested level change will oc- cur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossi ng. the zero cross function is independently monitored and implemented for each channel. soft ramp soft ramp allows level changes, either by gain chan ges, attenuation changes or muting, to be implement- ed by incrementally ramping, in 1/ 8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. 7654 3 210 dac_sngvol dac_szc1 dac_szc0 amute mute adc_sp adc_sngvol adc_szc1 adc_szc0
44 ds685f3 cs42435 soft ramp on zero crossing soft ramp and zero cross enable dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur in 1/ 8 db steps and be implemented on a signal zero cro ssing. the 1/8 db level change will occu r after a timeout period be tween 512 and 1024 sa mple periods (10. 7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encoun ter a zero crossing. the zero cross function is inde- pendently monitored and implemented for each channel. 7.7.3 auto-mute (amute) default = 1 0 - disabled 1 - enabled function: the digital-to-analog conv erters of the cs42435 will mute the outp ut following the reception of 8192 con- secutive audio samples of static 0 or -1. a single sa mple of non-static data will release the mute. detection and muting is done independently for each channel. the quiescent voltage on the outp ut will be retained during the mute period. the muting function is affected , similar to volume control changes, by the soft and zero cross bits (szc[1:0]). 7.7.4 mute adc serial port (mute adc_sp) default = 0 0 - disabled 1 - enabled function: when enabled, the adc se rial port will be muted. 7.8 dac channel mute (address 07h) 7.8.1 independent channel mute (aoutx_mute) default = 0 0 - disabled 1 - enabled function: the respective digital-to-analog converter outputs of the cs42435 will mute when enabled. the quies- cent voltage on the output s will be retained. the muting function is affected by the dac soft and zero cross bits (dac_szc[1:0]). 76543210 aout8_mute aout7_mute aout6_mute aout5_mute aout4_mute aout3_mute aout2_mute aout1_mute
ds685f3 45 cs42435 7.9 aoutx volume control (a ddresses 08h- 0fh) 7.9.1 volume contro l (aoutx_vol[7:0]) default = 00h function: the aoutx volume control registers allow independent setting of the signal levels in 0.5 db increments from 0 db to -127.5 db. volume settings are decoded as shown in table 6 . the volume changes are im- plemented as dictated by the soft and zero cross bi ts (dac_szc[1:0]). all volume settings less than - 127.5 db are equivalent to enabling the aoutx_mute bit for the given channel. 7.10 dac channel invert (address 10h) 7.10.1 invert signal polarity (inv_aoutx) default = 0 0 - disabled 1 - enabled function: when enabled, these bits will invert the si gnal polarity of their respective channels. 7.11 ainx volume c ontrol (address 11h-14h) 7.11.1 ainx volume control (ainx_vol[7:0]) default = 00h function: the level of the analog inputs can be adjusted in 0. 5 db increments as dictated by the adc soft and zero cross bits (adc_szc[1:0]) from +24 to -64 db. levels are decoded in two?s complement, as shown in table 7 . 76543210 aoutx_vol7 aoutx_vol6 aoutx_vol5 aoutx_vol4 aoutx_vol3 aoutx_vol2 aoutx_vol1 aoutx_vol0 binary code volume setting 00000000 0 db 00101000 -20 db 01010000 -40 db 01111000 -60 db 10110100 -90 db table 6. example aout volume settings 76543210 inv_aout8 inv_aout7 inv_aout6 inv_aout5 inv_aout4 inv_aout3 inv_aout2 inv_aout1 76543210 ainx_vol7 ainx_vol6 ainx_vol5 ainx_vol4 ainx_vol3 ainx_vol2 ainx_vol1 ainx_vol0
46 ds685f3 cs42435 7.12 adc channel invert (address 17h) 7.12.1 invert signal polarity (inv_ainx) default = 0 0 - disabled 1 - enabled function: when enabled, these bits will invert the signal polarity of their respective channels. 7.13 status (address 19h) (read only) for all bits in this register, a ?1? means the associated error condition has occurred at least once since the register was last read. a?0? means the associated er ror condition has not occurred since the last reading of the register. reading the register resets all bits to 0. status bits that are masked off in the associated mask register will always be ?0? in this register. 7.13.1 clock error (clk error) default = x function: indicates an invalid mclk to fs ratio. this status fl ag is set to ?level active mode? and becomes active during the error condition. see ?system clocking? on page 31 for valid clock ratios. 7.13.2 adc overflow (adcx_ovfl) default = x function: indicates that there is an over-range condition anyw here in the cs42435 adc signal path of each of the associated adc?s. binary code volume setting 0111 1111 +24 db 0011 0000 +24 db 0000 0000 0 db 1111 1111 -0.5 db 1111 1110 -1 db 1000 0000 -64 db table 7. example ain volume settings 76543210 reserved reserved reserved reserved inv_a4 inv_a3 inv_a2 inv_a1 765 4 3 2 1 0 reserved reserved reserved reserved clk error reserved adc2_ovfl adc1_ovfl
ds685f3 47 cs42435 7.14 status mask (address 1ah) default = 0000 function: the bits of this register serve as a mask for the error sources found in the register ?status (address 19h) (read only)? on page 46 . if a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status register. if a mask bit is set to 0, the error is masked, meanin g that its occurrence will not affect status register. the bit positions align wit h the corresponding bits in the status register. 765 4 32 1 0 reserved reserved reserved reserved clk error_m reserved adc2_ovfl_m adc1_ovfl_m
48 ds685f3 cs42435 8. external filters 8.1 adc input filter the analog modulator samples the input at 6.144 mhz (internal mclk=12.288 mhz). the digital filter will reject signals within the stopband of the filter. howeve r, there is no rejection for input signals which are mul- tiples of the digital passband frequency (n ? 6.144 mhz), where n=0,1,2,... refer to figures 19 and 20 for a recommended analog input filter that will attenuate any noise energy at 6. 144 mhz, in addition to providing the optimum source impedance for the modulators. refer to figures 21 and 22 for low-cost, low-component- count passive input filters. the use of capacitors that have a large voltage coeffi cient (such as general-pur- pose ceramics) must be avoided si nce these can degrade signal linearity va + + - - 4.7 ? f 100 k ? 10 k ? 100 k ? 100 k ? 0.1 ? f100 ? f 470 pf 470 pf c0g c0g 634 ? 634 ? 634 ? 91 ? 91 ? 2700 pf c0g 332 ? ainx+ ainx- adc1-2 figure 19. single-to-differential active input filter - + 470 pf c0g 634 ? 91 ? 2700 pf c0g 4.7 ? f 100 k ? 100 k ? 100 k ? va 4.7 ? f ain1+,2+,3+,4+ ain1-,2-,3-,4- adc1-2 figure 20. single-ended active input filter
ds685f3 49 cs42435 8.1.1 passive input filter the passive filter implementation shown in figure 21 will attenuate any noise energy at 6.144 mhz but will not provide optimum source impedance for the adc modulators. full analog performance will there- fore not be realized using a passive filter. figure 21 illustrates the unity gain, pa ssive input filter solution. in this topology the distortion performance is affected, but the dynamic range performance is not limited. 8.1.2 passive input filter w/attenuation some applications may require sig nal attenuation prior to the adc. the full-scale input voltage will scale with the analog power supply voltage. for va = 5. 0 v, the full-scale input voltage is approximately 2.8 vpp, or 1 vrms (most consumer audio line- level outputs range from 1.5 to 2 vrms). figure 22 shows a passive input filter with 6 db of signal at tenuation. due to the relatively high input im- pedance on the analog inputs, the full distortion perform ance cannot be realized. also, the resistor divider circuit will determine the input impedance into the input filt er. in the circuit shown in figure 22 , the input impedance is approximately 5 k ?? by doubling the resistor values , the input impedan ce will increase to 10 k ?? however, in this case the distor tion performance will drop due to the increase in series resistance on the analog inputs. 2700 pf c0g 10 ? f 100 k ? 150 ? ain1+,2+,3+,4+ ain1-,2-,3-,4- adc1-2 4.7 ? f figure 21. passive input filter 2700 pf c0g 10 ? f 2.5 k ? ain1+,2+,3+,4+ ain1-,2-,3-,4- adc1-2 4.7 ? f 2.5 k ? figure 22. passive input filter w/attenuation
50 ds685f3 cs42435 8.2 dac output filter the recommended active and passive output filters are shown below. aoutx + aoutx - - + 390 pf c0g 562? 22 ? f 4.75 k ? 1800 pf c0g 887 ? 2.94 k ? 5.49 k ? 1.65 k ? 1.87 k ? 22 ? f 1200 pf c0g 5600 pf c0g 47.5 k ? dac1-4 figure 23. active analog output filter aoutx+ 3.3 f c 560 ? + 10 k ? r ext r ext + 560 c= 4 ? f s r ext 560 dac1-4 figure 24. passive analog output filter
ds685f3 51 cs42435 9. adc filter plots figure 25. ssm stopband rejection figure 26. ssm transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (normalized to fs) amplitude (db) figure 27. ssm transition band (detail) figure 28. ssm passband ripple -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db ) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 29. dsm stopband rejection f igure 30. dsm transition band
52 ds685f3 cs42435 ? -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (norm alized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (normalized to fs) amplitude (db ) figure 31. dsm transition band (detai l) figure 32. dsm passband ripple
ds685f3 53 cs42435 10.dac filter plots figure 33. ssm stopband rejection figure 34. ssm transition band 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -0.25 -0. 2 -0.15 -0. 1 -0.05 0 0.05 frequency (normalized to fs) amplitude db figure 35. ssm transition band (detail) figure 36. ssm passband ripple figure 37. dsm stopband rejection figure 38. dsm transition band
54 ds685f3 cs42435 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -0. 2 -0. 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 frequency (normalized to fs) amplitude db figure 39. dsm transition band (det ail) figure 40. dsm passband ripple 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) figure 41. qsm stopband rejection figure 42. qsm transition band 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) 0.4 0.45 0.5 0.55 0.6 0.65 0.7 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 amplitude (db) frequency(normalized to fs) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -1. 5 -1 -0. 5 0 frequency (normalized to fs) amplitude db figure 43. qsm transition band (detail) figure 44. qsm passband ripple
ds685f3 55 cs42435 11.parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specified band width made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measure- ment. this measurement technique has been accept ed by the audio engineer ing society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified band width (typically 10 hz to 20 kh z), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right cha nnel pairs. measured for each channel at the convert- er's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channel pairs. units in decibels. gain error the deviation from the nominal full-scale an alog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv. 12.references 1. cirrus logic, techniques to measure and maximize the pe rformance of a 120 db, 96 khz a/d converter integrated circuit , by steven harris, steven green and ka leung . presented at the 103rd convention of the audio engineering society, september 1997. 2. cirrus logic, the effects of sampling clock jitter on nyquis t sampling analog-to-digital converters, and on oversampling delta sigma adc's , by steven harris. paper presented at the 87th convention of the au- dio engineering society, october 1989. 3. philips semiconductor, the i2c-bus specification: version 2.1 , january 2000. http://www.semicondu ctors.philips.com
56 ds685f3 cs42435 13.package information 13.1 thermal characteristics inches millimeters dim min nom max min nom max a --- --- 0.096 --- --- 2.45 a1 0.000 --- 0.010 0.00 --- 0.25 b 0.009 --- 0.016 0.22 --- 0.40 d --- 0.519 --- --- 13.20 bsc --- d1 --- 0.394 --- --- 10.00 bsc --- e --- 0.519 --- --- 13.20 bsc --- e1 --- 0.394 --- --- 10.00 bsc --- e* --- 0.026 --- --- 0.65 bsc --- l 0.029 0.035 0.041 0.73 0.88 1.03 0.00 4 7.00 0.00 4 7.00 * nominal pin pitch is 0.65 mm controlling dimension is mm. jedec designation: ms022 parameter symbol min typ max units junction to ambient thermal impedance 2 layer board 4 layer board ? ja ? ja - - 47 38 - - c/watt c/watt e1 e d1 d 1 e l ? b a1 a 52l mqfp package drawing
ds685f3 57 cs42435 14.ordering information 15.revision history product description package pb-free grade temp range container order # cs42435 4-in, 8-out, tdm codec for surround sound apps 52l-mqfp yes commercial -40c to +85c rail CS42435-CMZ tape & reel CS42435-CMZr automotive -40c to +105c rail cs42435-dmz tape & reel cs42435-dmzr cdb42438 cs42438 evaluation board - - - - - cdb42438 revision changes f1 initial release f2 pin labels for pins 3 and 4 were corrected in figure 1. "pin descriptions - software mode" on page 6 . updated input impedance specification for differential and single-ended inputs in ?analog input characteris- tics (commercial)? section on page 14 and ?analog input characteristics (a utomotive)? section on page 15 . f3 added note 8 ?the input impedance scales inversely proportionate to the sample rate of the adc modulator? to ?analog input characteristics (a utomotive)? section on page 15 . contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com. important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life su pport products or other crit- ical applications. inclusion of cirrus products in such applications is under stood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with re gard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the us e of cirrus products in critical applic ations, custome r agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, includ- ing attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product name s in this document may be trademarks or service marks of their respective owners. i2c is a t rademark of philips semiconductor. spi is a trademark of motorola, inc.

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